MC68HC908LJ24 Datasheet, PDF (424/464 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Low-Voltage Inhibit (LVI)
22.4.1 Polled LVI Operation
In applications that can operate at V_DD levels below the V_TRIPF level,
software can monitor V_DD by polling the LVIOUT bit, or by setting the LVI
interrupt enable bit, LVIIE, to enable interrupt requests. In the
configuration register 1 (CONFIG1), the LVIPWRD bit must be at logic 0
to enable the LVI module, and the LVIRSTD bit must be at logic 1 to
disable LVI resets.
The LVI interrupt flag, LVIIF, is set whenever the LVIOUT bit changes
state (toggles). When LVIF is set, a CPU interrupt request is generated
if the LVIIE is also set. In the LVI interrupt service subroutine, LVIIF bit
can be cleared by writing a logic 1 to the LVI interrupt acknowledge bit,
LVIIACK.
22.4.2 Forced Reset Operation
In applications that require V_DD to remain above the V_TRIPF level,
enabling LVI resets allows the LVI module to reset the MCU when V_DD
falls below the V_TRIPF level. In the configuration register 1 (CONFIG1),
the LVIPWRD and LVIRSTD bits must be at logic 0 to enable the LVI
module and to enable LVI resets.
If LVIIE is set to enable LVI interrupts when LVIRSTD is cleared, LVI
reset has a higher priority over LVI interrupt. In this case, when V_DD falls
below the V_TRIPF level, an LVI reset will occur, and the LVIIE bit will be
cleared.
22.4.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having V_DD fall below V_TRIPF), the LVI
will maintain a reset condition until V_DD rises above the rising trip point
voltage, V_TRIPR. This prevents a condition in which the MCU is
continually entering and exiting reset if V_DD is approximately equal to
V_TRIPF. V_TRIPR is greater than V_TRIPF by the hysteresis voltage, V_HYS.
Data Sheet
424
MC68HC908LJ24/LK24 — Rev. 2
Low-Voltage Inhibit (LVI)
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