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MC68HC908LJ24 Datasheet, PDF (167/464 Pages) Motorola, Inc – Microcontrollers
Freescale Semiconductor, Inc.
Monitor ROM (MON)
Functional Description
10.4.1 Entering Monitor Mode
Table 10-1 shows the pin conditions for entering monitor mode. As
specified in the table, monitor mode may be entered after a POR and will
allow communication at 9600 baud provided one of the following sets of
conditions is met:
1. If $FFFE and $FFFF do not contain $FF (programmed state):
– The external clock is 4.9152 MHz with PTC1 low or
9.8304 MHz with PTC1 high
– IRQ = VTST (PLL off)
2. If $FFFE and $FFFF both contain $FF (erased state):
– The external clock is 9.8304 MHz
– IRQ = VDD (this can be implemented through the internal IRQ
pullup; PLL off)
3. If $FFFE and $FFFF both contain $FF (erased state):
– The external clock is 32.768 kHz (crystal)
– IRQ = VSS (this setting initiates the PLL to boost the external
32.768 kHz to an internal bus frequency of 2.4576 MHz)
If VTST is applied to IRQ and PTC1 is low upon monitor mode entry
(above condition set 1), the bus frequency is a divide-by-two of the input
clock. If PTC1 is high with VTST applied to IRQ upon monitor mode entry,
the bus frequency will be a divide-by-four of the input clock. Holding the
PTC1 pin low when entering monitor mode causes a bypass of a divide-
by-two stage at the oscillator only if VTST is applied to IRQ. In this event,
the CGMOUT frequency is equal to the CGMXCLK frequency, and the
OSC1 input directly generates internal bus clocks. In this case, the
OSC1 signal must have a 50% duty cycle at maximum bus frequency.
If entering monitor mode without high voltage on IRQ (above condition
set 2 or 3, where applied voltage is either VDD or VSS), then all port A pin
requirements and conditions, including the PTC1 frequency divisor
selection, are not in effect. This is to reduce circuit requirements when
performing in-circuit programming.
MC68HC908LJ24/LK24 — Rev. 2
MOTOROLA
Monitor ROM (MON)
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Data Sheet
167