MC68HC908LJ24 Datasheet, PDF (210/464 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Timer Interface Module (TIM)
PS[2:0] — Prescaler Select Bits
These read/write bits select one of the seven prescaler outputs as the
input to the TIM counter as Table 11-2 shows. Reset clears the
PS[2:0] bits.
Table 11-2. Prescaler Selection
PS2
PS1
PS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
TIM Clock Source
Internal bus clock ÷ 1
Internal bus clock ÷ 2
Internal bus clock ÷ 4
Internal bus clock ÷ 8
Internal bus clock ÷ 16
Internal bus clock ÷ 32
Internal bus clock ÷ 64
TCLK
11.10.2 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes
of the value in the TIM counter. Reading the high byte (TCNTH) latches
the contents of the low byte (TCNTL) into a buffer. Subsequent reads of
TCNTH do not affect the latched TCNTL value until TCNTL is read.
Reset clears the TIM counter registers. Setting the TIM reset bit (TRST)
also clears the TIM counter registers.
NOTE:
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL
by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
Data Sheet
210
Address: T1CNTH, $0021 and T2CNTH, $002C
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-5. TIM Counter Registers High (TCNTH)
MC68HC908LJ24/LK24 — Rev. 2
Timer Interface Module (TIM)
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