MC68HC908LJ24 Datasheet, PDF (212/464 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Timer Interface Module (TIM)
11.10.4 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers:
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input
capture trigger
• Selects output toggling on TIM overflow
• Selects 0% and 100% PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
Address: T1SC0, $0025 and T2SC0, $0030
Bit 7
6
5
4
3
2
1
Bit 0
Read: CH0F
Write: 0
CH0IE
MS0B
MS0A
ELS0B ELS0A
TOV0 CH0MAX
Reset: 0
0
0
0
0
0
0
0
Figure 11-9. TIM Channel 0 Status and Control Register (TSC0)
Address: T1SC1, $0028 and T2SC1, $0033
Bit 7
6
5
4
3
2
1
Bit 0
Read: CH1F
0
CH1IE
MS1A ELS1B ELS1A TOV1 CH1MAX
Write: 0
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-10. TIM Channel 1 Status and Control Register (TSC1)
Data Sheet
212
MC68HC908LJ24/LK24 — Rev. 2
Timer Interface Module (TIM)
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