MC68HC908LJ24 Datasheet, PDF (142/464 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
System Integration Module (SIM)
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SBSW
$FE00
SIM
Break
Status
Register
(SBSR)
Write:
R
R
R
R
R
R
R
Note
Reset:
0
Note: Writing a logic 0 clears SBSW.
Read: POR
PIN
COP ILOP ILAD
0
LVI
0
$FE01
SIM
Reset
Status
Register
(SRSR)
Write:
POR: 1
0
0
0
0
0
0
0
SIM Break Flag Control ^Read: _BCFE
R
R
R
R
R
R
R
$FE03
Register Write:
(SBFCR) _{Reset: 0}
Read: IF6
IF5
IF4
IF3
IF2
IF1
0
0
$FE04
Interrupt Status Register 1
(INT1)
Write:
R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
Read: IF14
IF13
IF12
IF11
IF10
IF9
IF8
IF7
$FE05
Interrupt Status Register 2
(INT2)
Write:
R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
Read: 0
0
0
0
IF18
IF17
IF16
IF15
$FE06
Interrupt Status Register 3
(INT3)
Write:
R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
R = Reserved
Figure 9-2. SIM I/O Register Summary
9.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in Figure 9-3. This clock can come
from either the oscillator module or from the on-chip PLL. (See Section
8. Clock Generator Module (CGM).)
Data Sheet
142
MC68HC908LJ24/LK24 — Rev. 2
System Integration Module (SIM)
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