MC68HC908LJ24 Datasheet, PDF (207/464 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Timer Interface Module (TIM)
I/O Signals
11.9 I/O Signals
Port B shares four of its pins with the TIM channel I/O pins: T1CH0,
T1CH1, T2CH0, and T2CH1.
Port D shares two of its pins with the TIM clock input pins: T1CLK and
T2CLK
11.9.1 TIM Clock Pins (PTD4/KBI4/T1CLK, PTD5/KBI5/T2CLK)
T[1,2]CLK is an external clock input that can be the clock source for the
TIM[1,2] counter instead of the prescaled internal bus clock. Select the
T[1,2]CLK input by writing logic 1’s to the three prescaler select bits,
PS[2:0]. (See 11.10.1 TIM Status and Control Register.) The minimum
T[1,2]CLK pulse width, T[1,2]CLK_LMIN or T[1,2]CLK_HMIN, is:
------------------1-------------------
bus frequency
+
t_SU
The maximum T[1,2]CLK frequency is:
bus frequency ÷ 2
T1CLK and T2CLK are available as standard I/Os or KBI pins when not
used as the TIM clock inputs.
11.9.2 TIM Channel I/O Pins (PTB2/T1CH0, PTB3/T1CH1, PTB4/T2CH0, PTB5/T2CH1)
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. T1CH0 and T2CH0 can be
configured as buffered output compare or buffered PWM pins.
MC68HC908LJ24/LK24 — Rev. 2
MOTOROLA
Timer Interface Module (TIM)
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Data Sheet
207