MC68HC908LJ24 Datasheet, PDF (236/464 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Real Time Clock (RTC)
NOTE:
With compensation enabled, the RTC clock and calendar register
updates may not be synchronized to the timebase and chronograph
clocks, since their clocks are derived from the uncompensated
CGMXCLK.
Hence, time intervals for timebase ticks may not align with the RTC clock
and calendar register updates.
CHRCLR — Chronograph counter clear
Setting this write-only bit resets the chronograph counter and the
chronograph data register (CHRR). Setting CHRCLR has no effect on
any other registers. Counting resumes from $00. CHRCLR is cleared
automatically after the chronograph counter is reset and always reads
as logic 0. Reset clears the CHRCLR bit.
1 = Chronograph counter cleared
0 = No effect
CHRE — Chronograph Enable
This read/write bit enables the chronograph counter. When the
chronograph counter is disabled (CHRE = 0), the value in the
chronograph data register is held at the count value. Reset clears the
CHRE bit.
1 = Chronograph counter enabled
0 = Chronograph counter disabled
RTCE — Real Time Clock Enable
This read/write bit enables the entire RTC module, allowing all RTC
and chronograph operations. Disabling the RTC module does not
affect the contents in the RTC registers. Reset clears the RTCE bit.
1 = RTC module enabled
0 = RTC module disabled
TBH — Timebase High Frequency Select
This read/write bit selects the timebase interrupt period for TB1 and
TB2. Reset clears the TBH bit.
1 = TB1 interrupt is 0.125s; TB2 interrupt is 0.0625s
0 = TB1 interrupt is 0.5s; TB2 interrupt is 0.25s
Data Sheet
236
MC68HC908LJ24/LK24 — Rev. 2
Real Time Clock (RTC)
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