MC68HC908LJ24 Datasheet, PDF (370/464 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Liquid Crystal Display (LCD) Driver
17.9.2 LCD Clock Register (LCDCLK)
The LCD clock register (LCDCLK):
• Selects the fast charge duty cycle
• Selects LCD driver duty cycle
• Selects LCD waveform base clock
Address: $004F
Bit 7
6
5
4
3
2
1
Read: 0
Write:
FCCTL1 FCCTL0 DUTY1 DUTY0 LCLK2 LCLK1
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 17-17. LCD Clock Register (LCDCLK)
Bit 0
LCLK0
0
FCCTL[1:0] — Fast Charge Duty Cycle Select
These read/write bits select the duty cycle of the fast charge duration.
Reset clears these bits. (See 17.5.4 Fast Charge and Low Current)
Table 17-4. Fast Charge Duty Cycle Selection
FCCTL1:FCCTL0
00
01
10
11
Fast Charge Duty Cycle
In each LCDCLK/2 period, each bias resistor is reduced to
37 kΩ for a duration of LCDCLK/32.
In each LCDCLK/2 period, each bias resistor is reduced to
37 kΩ for a duration of LCDCLK/64.
In each LCDCLK/2 period, each bias resistor is reduced to
37 kΩ for a duration of LCDCLK/128.
Not used
Data Sheet
370
MC68HC908LJ24/LK24 — Rev. 2
Liquid Crystal Display (LCD) Driver
For More Information On This Product,
Go to: www.freescale.com
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