MC68HC908LJ24 Datasheet, PDF (345/464 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Analog-to-Digital Converter (ADC)
I/O Registers
In left justified mode the ADRH holds the eight most significant bits
(MSBs), and the ADRL holds the two least significant bits (LSBs), of the
10-bit result. The ADRH and ADRL are updated each time a single
channel ADC conversion completes. Reading ADRH latches the
contents of ADRL. Until ADRL is read all subsequent ADC results will be
lost. (See Figure 16-7 . ADRH and ADRL in Left Justified Mode.)
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
$003D
ADC Data Register High
(ADRH)
Write:
R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
Read: AD1
AD0
0
0
0
0
0
0
$003E
ADC Data Register Low
(ADRL)
Write:
R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
Figure 16-7. ADRH and ADRL in Left Justified Mode
In left justified sign mode the ADRH holds the eight MSBs with the MSB
complemented, and the ADRL holds the two least significant bits (LSBs),
of the 10-bit result. The ADRH and ADRL are updated each time a single
channel ADC conversion completes. Reading ADRH latches the
contents of ADRL. Until ADRL is read all subsequent ADC results will be
lost. (See Figure 16-8 . ADRH and ADRL in Left Justified Sign Data
Mode.)
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
$003D
ADC Data Register High
(ADRH)
Write:
R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
Read: AD1
AD0
0
0
0
0
0
0
$003E
ADC Data Register Low
(ADRL)
Write:
R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
Figure 16-8. ADRH and ADRL in Left Justified Sign Data Mode
MC68HC908LJ24/LK24 — Rev. 2
MOTOROLA
Analog-to-Digital Converter (ADC)
For More Information On This Product,
Go to: www.freescale.com
Data Sheet
345