MC68HC908LJ24 Datasheet, PDF (29/464 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
List of Figures
Figure
Title
Page
14-10 Clearing SPRF When OVRF Interrupt Is Not Enabled . . . . . . 302
14-11 SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . . . . 305
14-12 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
14-13 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . . 312
14-14 SPI Status and Control Register (SPSCR) . . . . . . . . . . . . . . . 314
14-15 SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
MMIIC I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . 321
Multi-Master IIC Address Register (MMADR). . . . . . . . . . . . . 321
Multi-Master IIC Control Register (MMCR). . . . . . . . . . . . . . . 323
Multi-Master IIC Master Control Register (MIMCR) . . . . . . . . 324
Multi-Master IIC Status Register (MMSR) . . . . . . . . . . . . . . . 326
Multi-Master IIC Data Transmit Register (MMDTR) . . . . . . . . 328
Multi-Master IIC Data Receive Register (MMDRR) . . . . . . . . 329
Data Transfer Sequences for Master/Slave
Transmit/Receive Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 331
16-1
16-2
16-3
16-4
16-5
16-6
16-7
16-8
16-9
ADC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 335
ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
8-Bit Truncation Mode Error . . . . . . . . . . . . . . . . . . . . . . . . . . 339
ADC Status and Control Register (ADSCR) . . . . . . . . . . . . . . 342
ADRH and ADRL in 8-Bit Truncated Mode. . . . . . . . . . . . . . . 344
ADRH and ADRL in Right Justified Mode. . . . . . . . . . . . . . . . 344
ADRH and ADRL in Left Justified Mode . . . . . . . . . . . . . . . . . 345
ADRH and ADRL in Left Justified Sign Data Mode . . . . . . . . 345
ADC Clock Control Register (ADCLK) . . . . . . . . . . . . . . . . . . 346
17-1 LCD I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 351
17-2 LCD Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
17-3 Simplified LCD Schematic (1/3 Duty, 1/3 Bias) . . . . . . . . . . . 354
17-4 Fast Charge Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
17-5 Static LCD Backplane Driver Waveform. . . . . . . . . . . . . . . . . 359
17-6 1/3 Duty LCD Backplane Driver Waveforms. . . . . . . . . . . . . . 359
17-7 1/4 Duty LCD Backplane Driver Waveforms. . . . . . . . . . . . . . 360
17-8 Static LCD Frontplane Driver Waveforms. . . . . . . . . . . . . . . . 361
17-9 1/3 Duty LCD Frontplane Driver Waveforms . . . . . . . . . . . . . 362
17-10 1/4 Duty LCD Frontplane Driver Waveforms . . . . . . . . . . . . . 363
MC68HC908LJ24/LK24 — Rev. 2
MOTOROLA
List of Figures
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Data Sheet
29