MC68HC908LJ24 Datasheet, PDF (82/464 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Configuration Registers (CONFIG)
SSREC — Short Stop Recovery
SSREC enables the CPU to exit stop mode with a delay of 32 ICLK
cycles instead of a 4096 ICLK cycle delay.
1 = Stop mode recovery after 32 ICLK cycles
0 = Stop mode recovery after 4096 ICLK cycles
NOTE:
NOTE:
Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal oscillator, do not set the SSREC bit.
When the LVISTOP is enabled, the system stabilization time for power
on reset and long stop recovery (both 4096 ICLK cycles) gives a delay
longer than the enable time for the LVI. There is no period where the
MCU is not protected from a low power condition. However, when using
the short stop recovery configuration option, the 32 ICLK delay is less
than the LVI’s turn-on time and there exists a period in start-up where the
LVI is not protecting the MCU.
STOP — STOP Instruction Enable
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. (See Section 21. Computer
Operating Properly (COP).)
1 = COP module disabled
0 = COP module enabled
5.5 Configuration Register 2 (CONFIG2)
The CONFIG2 register can be written once after each reset.
Address: $001D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PEE
Write:
Reset: 0
STOP_
IRCDIS
STOP_
XCLKEN
DIV2CLK
PCEH
0
0
0
0
PCEL LVISEL1 LVISEL0
0
0^††
1^††
†† Reset by POR only.
Figure 5-3. Configuration Register 2 (CONFIG2)
Data Sheet
82
MC68HC908LJ24/LK24 — Rev. 2
Configuration Registers (CONFIG)
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