MC68HC908LJ24 Datasheet, PDF (371/464 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Liquid Crystal Display (LCD) Driver
I/O Registers
DUTY[1:0] — Duty Cycle Select
These read/write bits select the duty cycle of the LCD driver output
waveforms. The multiplexed FP0/BP3 pin is controlled by the duty
cycle selected. Reset clears these bits.
Table 17-5. LCD Duty Cycle Selection
DUTY1:DUTY0
00
01
10
11
Description
Static selected; FP0/BP3 pin function as FP0.
1/3 duty cycle selected; FP0/BP3 pin functions as FP0.
1/4 duty cycle selected; FP0/BP3 pin functions as BP3.
Not used
LCLK[2:0] — LCD Waveform Base Clock Select
These read/write bits selects the LCD waveform base clock. Reset
clears these bits.
Table 17-6. LCD Waveform Base Clock Selection
LCLK2
LCLK1
LCLK0
Divide
Ratio
LCD Waveform Base
Clock Frequency
LCDCLK (Hz)
f_XTAL =
f_XTAL =
32.768kHz 4.9152MHz
LCD Frame Rate
f_XTAL(1) =
32.768 kHz
1/3
duty
1/4
duty
0
0
0
128
256
—
85.3
64
0
0
1
256
128
—
42.7
32
0
1
0
512
64
—
21.3
16
0
1
1
1024
32
—
10.7
8
1
0
0
16384
—
300
—
—
1
0
1
32768
—
150
—
—
1
1
0
65536
—
75
—
—
1
1
1
Reserved
Notes:
1. f_XTAL is the same as CGMXCLK (see Section 7. Oscillator (OSC)).
LCD Frame Rate
f_XTAL =
4.9152 MHz
1/3
duty
1/4
duty
—
—
—
—
—
—
—
—
100
75
50
37.5
25
18.75
MC68HC908LJ24/LK24 — Rev. 2
MOTOROLA
Liquid Crystal Display (LCD) Driver
For More Information On This Product,
Go to: www.freescale.com
Data Sheet
371