MC68HC908LJ24 Datasheet, PDF (150/464 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
System Integration Module (SIM)
9.6 Exception Control
Normal, sequential program execution can be changed in three different
ways:
• Interrupts:
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
• Reset
• Break interrupts
9.6.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume. Figure 9-8 shows interrupt entry timing, and
Figure 9-9 shows interrupt recovery timing.
MODULE
INTERRUPT
I-BIT
IAB
IDB
DUMMY
SP
SP – 1 SP – 2 SP – 3 SP – 4 VECT H VECT L START ADDR
DUMMY PC – 1[7:0] PC – 1[15:8] X
A
CCR V DATA H V DATA L OPCODE
R/W
Figure 9-8. Interrupt Entry Timing
MODULE
INTERRUPT
I-BIT
IAB
SP – 4 SP – 3 SP – 2 SP – 1
SP
PC
PC + 1
IDB
CCR
A
X PC – 1[15:8] PC – 1[7:0] OPCODE OPERAND
R/W
Figure 9-9. Interrupt Recovery Timing
Data Sheet
150
MC68HC908LJ24/LK24 — Rev. 2
System Integration Module (SIM)
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