MC68HC908LJ24 Datasheet, PDF (235/464 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Real Time Clock (RTC)
RTC Registers
SECIE — Second Interrupt Enable
This read/write bit enables the second flag, SECF, to generate CPU
interrupt requests. Reset clears the SECIE bit.
1 = SECF enabled to generate CPU interrupt
0 = SECF not enabled to generate CPU interrupt
TB1IE — Timebase 1 Interrupt Enable
This read/write bit enables the timebase1 flag, TB1F, to generate
CPU interrupt requests. Reset clears the TB1IE bit.
1 = TB1F enabled to generate CPU interrupt
0 = TB1F not enabled to generate CPU interrupt
TB2IE — Timebase 2 Interrupt Enable
This read/write bit enables the timebase2 flag, TB2F, to generate
CPU interrupt requests. Reset clears the TB2IE bit.
1 = TB2F enabled to generate CPU interrupt
0 = TB2F not enabled to generate CPU interrupt
12.10.4 RTC Control Register 2 (RTCCR2)
The RTC control register 2 (RTCCR2) contains control and clock
selection bits for RTC operation.
Address: $0043
Read:
0
0
0
0
COMEN*
CHRE RTCE* TBH
Write:
CHRCLR
Reset: U
0
0
0^††
0
0
0
0
= Unimplemented
†† Reset by POR only.
* COMEN and RTCE bits are write-protected; unprotect by a write sequence to RTCWE[1:0] in RTCCOMR.
Figure 12-9. RTC Control Register 2 (RTCCR2)
COMEN — RTC Compensation Enable
This read/write bit enables the clock compensation mechanism for
CGMXCLK frequency errors. Reset has no effect on COMEN bit.
1 = Compensation mechanism enabled
0 = Compensation mechanism not enabled
MC68HC908LJ24/LK24 — Rev. 2
MOTOROLA
Real Time Clock (RTC)
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Data Sheet
235