MC68HC908LJ24 Datasheet, PDF (118/464 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
The following conditions apply when in manual mode:
• ACQ is a writable control bit that controls the mode of the filter.
Before turning on the PLL in manual mode, the ACQ bit must be
clear.
• Before entering tracking mode (ACQ = 1), software must wait a
given time, t_ACQ (See 8.9 Acquisition/Lock Time
Specifications.), after turning on the PLL by setting PLLON in the
PLL control register (PCTL).
• Software must wait a given time, t_AL, after entering tracking mode
before selecting the PLL as the clock source to CGMOUT
(BCS = 1).
• The LOCK bit is disabled.
• CPU interrupts from the CGM are disabled.
8.4.6 Programming the PLL
The following procedure shows how to program the PLL.
NOTE: The round function in the following equations means that the real
number should be rounded to the nearest integer number.
1. Choose the desired bus frequency, f_BUSDES.
2. Calculate the desired VCO frequency, f_VCLKDES.
× f_VCLKDES = 2^P × f_CGMPCLK = 2^P × 4 f_BUSDES
where P is the power of two multiplier, and can be 0, 1, 2, or 3
3. Choose a practical PLL reference frequency, f_RCLK, and the
reference clock divider, R. Typically, the reference is 32.768kHz
and R = 1.
Frequency errors to the PLL are corrected at a rate of f_RCLK/R. For
stability and lock time reduction, this rate must be as fast as
possible. The VCO frequency must be an integer multiple of this
rate.
Data Sheet
118
MC68HC908LJ24/LK24 — Rev. 2
Clock Generator Module (CGM)
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