MC68HC908LJ24 Datasheet, PDF (166/464 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Monitor ROM (MON)
RST
0.1 µF
V_DD
HC908LJ24
0.1 µF
V_{DD 4.9152MHz/9.8304MHz}
(50% DUTY)
OSC1
V_DD
V_DDA
V_LCD
V_REFH
V_SS
V_REFL
CGMXFC
10 k
0.01 µF
MUST BE USED IF SW2 IS AT POSITION C.
CONNECT TO OSC1, WITH OSC2 UNCONNECTED.
0.033 µF
EXT OSC
32.768 kHz
1 µF
1 µF
DB9
2
3
5
MAX232
1 _C1+
+
3 _C1–
V_CC ¹⁶
GND ¹⁵
4 _C2+
+
5 _C2–
2
V+
V– ⁶
7
10
8
9
6–30 pF
V_DD
+
1 µF
1 µF
+
XTAL CIRCUIT
V_TST
V_{DD 1 k}
1 µF
+
10 k
74HC125
6
5
74HC125
2
3
4
1
330 k
6–30 pF
C
SW2
(SEE NOTE 1)
8.5 V
D
V_DD
10 k
V_DD
10 k
NOTES:
1. Monitor mode entry method:
SW2: Position C — High voltage entry (V_TST); must use external OSC
Bus clock depends on SW1 (note 2).
SW2: Position D — Reset vector must be blank ($FFFE:$FFFF = $FF)
Bus clock = 2.4576MHz.
2. Affects high voltage entry to monitor mode only (SW2 at position C):
SW1: Position A — Bus clock = OSC1 ÷ 4
SW1: Position B — Bus clock = OSC1 ÷ 2
5. See Table 24-4 for V_TST voltage level requirements.
A
(SEE NOTE 2)
B
10 k
SW1
10 k
OSC1
OSC2
IRQ
PTA0
PTA1
PTC1
PTA2
Figure 10-1. Monitor Mode Circuit
Data Sheet
166
MC68HC908LJ24/LK24 — Rev. 2
Monitor ROM (MON)
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA