MC68HC908LJ24 Datasheet, PDF (422/464 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Low-Voltage Inhibit (LVI)
Addr.
Register Name
Bit 7
6
5
4
3
2
Low-Voltage Inhibit Status ^{Read: LVIOUT} _LVIIE
LVIIF
0
0
0
$FE0F
Register Write:
LVIIACK
(LVISR) _{Reset: 0}
0
0
0
0
0
= Unimplemented
Figure 22-1. LVI I/O Register Summary
1
Bit 0
0
0
0
0
22.4 Functional Description
Figure 22-2 shows the structure of the LVI module.
V_DD
DEFAULT
ENABLED
LVIPWRD
FROM CONFIG1
STOP INSTRUCTION
FROM CONFIG1
LVIRSTD
LVISTOP
FROM CONFIG1
LOW V_DD
DETECTOR
LVISEL[1:0]
FROM CONFIG2
V_DD > V_TRIPR = 0
V_DD ≤ V_TRIPF = 1
FROM LVISR
LVIIE
EDGE
DETECT
LATCH _CLR
LVI RESET
LVI
INTERRUPT
REQUEST
LVIOUT
TO LVISR
LVIIACK
LVIIF
FROM LVISR TO LVISR
Figure 22-2. LVI Module Block Diagram
The LVI is enabled out of reset. The LVI module contains a bandgap
reference circuit and comparator. Clearing the LVI power disable bit,
LVIPWRD, enables the LVI to monitor V_DD voltage. Clearing the LVI
reset disable bit, LVIRSTD, enables the LVI module to generate a reset
when V_DD falls below a voltage, V_TRIPF. Setting the LVI enable in stop
mode bit, LVISTOP, enables the LVI to operate in stop mode.
Data Sheet
422
MC68HC908LJ24/LK24 — Rev. 2
Low-Voltage Inhibit (LVI)
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