MC68HC908LJ24 Datasheet, PDF (113/464 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
Functional Description
Addr.
Register Name
Bit 7
6
5
4
$0036
Read:
PLL Control Register
(PTCL)
Write:
Reset:
PLLIE
0
PLLF
PLLON BCS
0
1
0
Read:
LOCK
0
PLL Bandwidth Control
AUTO
ACQ
$0037
Register Write:
(PBWC)
Reset: 0
0
0
0
Read: 0
0
0
0
PLL Multiplier Select
$0038
Register High Write:
(PMSH)
Reset: 0
0
0
0
$0039
Read:
PLL Multiplier Select
Register Low Write:
(PMSL)
Reset:
MUL7
0
MUL6
1
MUL5
0
MUL4
0
$003A
Read:
PLL VCO Range Select
Register Write:
(PMRS)
Reset:
VRS7
0
VRS6
1
VRS5
0
VRS4
0
Read: 0
0
0
0
PLL Reference Divider
$003B
Select Register Write:
(PMDS)
Reset: 0
0
0
0
= Unimplemented
NOTES:
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
3
2
1
PRE1 PRE0 VPR1
0
0
0
0
0
0
0
0
0
MUL11 MUL10 MUL9
0
0
0
MUL3 MUL2 MUL1
0
0
0
VRS3 VRS2 VRS1
0
0
0
RDS3 RDS2 RDS1
0
0
0
R = Reserved
Figure 8-2. CGM I/O Register Summary
Bit 0
VPR0
0
R
0
MUL8
0
MUL0
0
VRS0
0
RDS0
1
MC68HC908LJ24/LK24 — Rev. 2
MOTOROLA
Clock Generator Module (CGM)
For More Information On This Product,
Go to: www.freescale.com
Data Sheet
113