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MC68HC908LJ24 Datasheet, PDF (146/464 Pages) Motorola, Inc – Microcontrollers | |||
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Freescale Semiconductor, Inc.
System Integration Module (SIM)
IRST
RST
RST PULLED LOW BY MCU
32 CYCLES
32 CYCLES
ICLK
IAB
Figure 9-5. Internal Reset Timing
The COP reset is asynchronous to the bus clock.
VECTOR HIGH
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
POR
INTERNAL RESET
Figure 9-6. Sources of Internal Reset
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
9.4.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module
(POR) generates a pulse to indicate that power-on has occurred. The
external reset pin (RST) is held low while the SIM counter counts out
4096 + 32 ICLK cycles. Thirty-two ICLK cycles later, the CPU and
memories are released from reset to allow the reset vector sequence to
occur.
At power-on, these events occur:
⢠A POR pulse is generated.
⢠The internal reset signal is asserted.
⢠The SIM enables CGMOUT.
⢠Internal clocks to the CPU and modules are held inactive for 4096
ICLK cycles to allow stabilization of the oscillator.
⢠The RST pin is driven low during the oscillator stabilization time.
⢠The POR bit of the SIM reset status register (SRSR) is set and all
other bits in the register are cleared.
Data Sheet
146
MC68HC908LJ24/LK24 â Rev. 2
System Integration Module (SIM)
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
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