RG82855GMESL72L Datasheet, PDF (99/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
Bit
11
10
9:1
0
Description
Rcven DLL shutdown disable:
0 = Normal operation. RCVEN DLL is turned off when the corresponding SO-DIMM is unpopulated.
1 = RCVEN DLL is turned on irrespective of SO-DIMM population.
ECC SO-DIMM Clock tri-state Disable:
0 = When DDR SDRAM ECC is not enabled, the ECC clocks (i.e., SCK2/SCK2#, SCK5/SCK5#,) are
tri- stated.
1 = When DDR SDRAM ECC is enabled, the ECC clocks (i.e., SCK2/SCK2#, SCK5/SCK5#,) are
treated just like the other clocks.
Reserved
Power State S1/S3 Refresh Control:
0 = Normal Operation, Pending refreshes are not completed before entering Self Refresh for S1/S3.
1 = All Pending Refreshes plus one extra is performed before entering Self Refresh for S1/S3.
4.9.16
DRC – DRAM Controller Mode Register (Device #0)
Address Offset:
Default Value:
Access:
Size:
70-73h
00000081h
RO, Read/Write
32 bits
Bit
31:30
29
28:24
23:22
21:20
Description
Revision Number (REV): Reflects the revision number of the format used for DDR SDRAM register
definition (Read Only).
Initialization Complete (IC): This bit is used for communication of software state between the Memory
Controller and the BIOS. BIOS sets this bit to 1 after initialization of the DDR SDRAM Memory Array is
complete. Setting this bit to a 1 enables DDR SDRAM Refreshes. On power up and S3 exit, the BIOS
initializes the DDR SDRAM array and sets this bit to a 1. This bit works in combination with the RMS bits
in controlling Refresh state:
IC Refresh State
0 OFF
1 ON
Reserved
Number of Channels (CHAN): Reflects that GMCH supports only one system memory channel.
00
One channel is populated appropriately
Others: Reserved
DDIM DDR SDRAM Data Integrity Mode:
00: No-ECC. No read-merge-write on partial writes. ECC data sense-amps are disabled and the data
output
is tristate (Default).
01: ECC
XX: Reserved
Datasheet
99