RG82855GMESL72L Datasheet, PDF (86/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
4.9
Intel^® 855GM/GME GMCH Main Memory Control,
Memory I/O Control Registers (Device #0, Function
#1)
The following table shows the GMCH Configuration Space for Device #0, Function #1. See
Section 4.2f or access nomenclature.
Table 27. Host-Hub I/F Bridge/System Memory Controller Configuration Space (Device #0,
Function#1)
Register Name
Vendor Identification
Device Identification
PCI Command
PCI Status
Revision Identification
Sub-Class Code
Base Class Code
Header Type
Subsystem Vendor Identification
Subsystem Identification
Capabilities Pointer
DRAM Row 0-3 Boundary
DRAM Row 0-3 Attribute
DRAM Timing
DRAM Controller Power
Management Control
Dram Controller Mode
DRAM Throttle Control
Register
Symbol
VID
DID
PCICMD
PCISTS
RID
SUBC
BCC
HDR
SVID
SID
CAPPTR
DRB
DRA
DRT
PWRMG
DRC
DTC
Register
Start
00
02
04
06
08
0A
0B
0E
2C
2E
34
40
50
60
68
Register
End
01
03
05
07
08
0A
0B
0E
2D
2F
34
43
51
63
6B
Default Value
Access
8086h
3584h
0006h
0080h
02h
80h
08h
80h
0000h
0000h
00h
00000000h
7777h
18004425h
00000000h
RO
RO
RO,R/W
RO,R/WC
RO
RO
RO
RO
R/WO
R/WO
RO
RW
RW
RW
R/W
70
73
00000081h
R/W
A0
A3
00000000h
R/W/L
86
Datasheet