RG82855GMESL72L Datasheet, PDF (138/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Functional Description
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6.2.2
6.3
6.3.1
In a GMCH platform, the ICH4-M contains IOxAPICs and its interrupts are generated as
upstream Hub interface Memory Writes. Furthermore, PCI 2.2 defines MSI’s (Message Signaled
Interrupts) that are also in the form of Memory Writes. A PCI 2.2 device may generate an
interrupt as an MSI cycle on its PCI bus instead of asserting a hardware signal to the IOxAPIC.
The MSI may be directed to the IOxAPIC, which in turn generates an interrupt as an upstream
Hub interface memory write. Alternatively the MSI may be directed directly to the system bus.
The target of an MSI is dependent on the address of the interrupt Memory Write. The GMCH
forwards inbound Hub interface memory writes to address 0FEEx_xxxxh, to the system bus as
Interrupt Message transactions.
Upstream Interrupt Messages
The GMCH accepts message based interrupts from its Hub interface and forwards them to the
system bus as Interrupt Message transactions. The Interrupt Messages presented to the GMCH are
in the form of Memory Writes to address 0FEEx_xxxxh. At the Hub interface, the Memory Write
Interrupt Message is treated like any other Memory Write; it is either posted into the inbound data
buffer (if space is available) or retried (if data buffer space is not immediately available). Once
posted, the Memory Write from the Hub interface, to address 0FEEx_xxxxh, is decoded as a
cycle that needs to be propagated by the GMCH to the front side bus as an Interrupt Message
transaction.
System Memory Interface
DDR SDRAM Interface Overview
The GMCH supports DDR SDRAM at 200/266 MHz and includes the following support:
• Up to 1 GB of PC1600/PC2100 DDR SDRAM
• Up to 2 GB (high density) of PC1600/PC2100 DDR SDRAM
• PC1600/2100 unbuffered 200-pin DDR SDRAM SO-DIMMs
• Configurable optional ECC
• Maximum of two SO-DIMMs, single-sided and/or double-sided
The 2-bank select lines SBA[1:0] and the 13 Address lines SMA[12:0] allow the GMCH to
support 64-bit wide SO-DIMMs using 128-Mb, 256-Mb, and 512-Mb DDR SDRAM technology.
While address lines SMA[9:0] determine the starting address for a burst, burst length can only be
4. Four chip selects SCS[3:0]# lines allow a maximum of two rows of single-sided DDR SDRAM
SO-DIMMs and four rows of double-sided DDR SDRAM SO-DIMMs.
The GMCH main system memory controller targets CAS latencies of 2 and 2.5 for DDR
SDRAM. The GMCH provides refresh functionality with a programmable rate (normal DDR
SDRAM rate is 1 refresh/15.6 s). For write operations of less than a full cache line, GMCH will
perform a cache-line read and into the write buffer and perform byte-wise write-merging in the
write buffer.
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Datasheet