RG82855GMESL72L Datasheet, PDF (78/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
4.8.24
SHIC – Secondary Host Interface Control Register (Device
#0)
Address Offset:
Default Value:
Access:
Size:
74-77h
00006010h
Read Only, Read/Write
32 bits
Bit
31
30
29:28
27
26:7
6
5
4:3
2
Description
Reserved
BREQ0# Control of FSB Address and Control bus power management:
0 = Disable FSB address and control bus power management.
1 = Enable FSB address and control bus power management.
Reserved
On Die Termination (ODT) Gating Disable:
0 = Enable.
1 = Disable.
Reserved
FSB Data Bus Power Management Control:
0 = FSB Data Bus Power Management disabled (Default).
1 = FSB Data Bus Power Management enabled
Reserved
DPWR# Control.
00 = DPWR# pin is always asserted.
10 = DPWR# pin is asserted at least 2 clocks before read data is returned to the processor on the FSB
(2 clocks before DRDY# asserted). This is default setting.
01 = DPWR# is always de-asserted.
11 = Reserved
C2 state GMCH FSB Interface Power Management Control:
0 = Power Management Disabled in C2 state
1 = Power Management Enabled in C2 state
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Datasheet