RG82855GMESL72L Datasheet, PDF (27/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

2.7
2.8
2.9
Intel® 855GM/855GME Chipset GMCH Overview
R
selected during system initialization. Both upstream and downstream addressing is limited to 32-
bits for AGP and AGP/PCI transactions. The GMCH/MCH contains a 32-deep AGP request
queue. High priority accesses are supported. All accesses from the AGP/PCI interface that fall
within the Graphics Aperture address range pass through an address translation mechanism with a
fully associative 20 entry TLB. Accesses between AGP and hub interface are limited to memory
writes originating from the hub interface destined for AGP. The AGP interface is clocked from a
dedicated 66 MHz clock (GLCKIN). The AGP-to-host/core interface is asynchronous.
The AGP interface should be powered-off or tri-stated without voltage on the interface during
ACPI S3 or APM Suspend to RAM state.
Refer to the AGP Busy and Stop Signals Specification for more information.
Hub Interface
A proprietary interconnect connects the GMCH to the ICH4-M. All communication between the
GMCH and the ICH4-M occurs over the Hub interface 1.5. The Hub interface runs at 66 MHz
(266-MB/s).
Address Decode Policies
Host initiated I/O cycles are positively decoded to the GMCH configuration space and
subtractively decoded to Hub interface. Host initiated system memory cycles are positively
decoded to DDR SDRAM and are again subtractively decoded to Hub interface if under 4 GB.
System memory accesses from Hub interface to DDR SDRAM will be snooped on the FSB.
GMCH Clocking
The GMCH has the following clock input/output pins:
• 400 MHz, spread spectrum, low voltage differential BCLK, BCLK# for front side bus (FSB)
• 66 MHz, 3.3 V GCLKIN for Hub interface buffers
• Six pairs of differential output clocks (SCK[5:0], SCK[5:0]#), 200/266 MHz, 2.5 V for
system memory interface
• 48 MHz, non-Spread Spectrum, 3.3 V DREFCLK for the Display Frequency Synthesis
• 48 MHz or 66 MHz, Spread Spectrum, 3.3 V DREFSSCLK for the Display Frequency
Synthesis
• Up to 85 MHz, 1.5 V DVOBCCLKINT for TV-Out mode
• DPMS clock for S1-M
Clock Synthesizer chips are responsible for generating the system host clocks, GMCH display
clocks, Hub interface clocks, PCI clocks, SIO clocks, and FWH clocks. The host target speed is
400 MHz. The GMCH does not require any relationship between the BCLK Host clock and the
66 MHz clock generated for Hub interface; they are asynchronous to each other. The Hub
interface runs at a constant 66 MHz base frequency. Table 2 indicates the frequency ratios
between the various interfaces that the GMCH supports.
Datasheet
27