RG82855GMESL72L Datasheet, PDF (83/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
Bit
Description
2
AGP/PCI1 Discard Timer Disable.
0 = Enable (default). Enables the Discard Timer for the delayed transactions on the PCI1/AGP
interface (initiated by the AGP agent using PCI protocol). The counter starts once the delayed
transaction request is ready to complete as far as GMCH is concerned (i.e., read data is pending on
the top of AGP Outbound queue). If the AGP agent (using PCI protocol) does not repeat the
transaction before the counter expires after 2^10 clocks (66 MHz) the GMCH will delete the delayed
transaction from its queue and set the Discard Timer Status bit.
1 = Disable. The discard timer is disabled.
1
AGP/PCI Discard Timer Status (AGPDTS): R/WC When set to 1 this bit indicates that a delayed
transaction on PCI_B has been discarded due to DT timer expiration. When set this bit can be cleared
by writing it with 1.
0
Reserved
4.8.30
APSIZE – Aperture Size (Device #0)
Address Offset:
Default Value:
Access:
Size:
B4h
00h
Read/Write
8 bits
This register determines the effective size of the Graphics Aperture used for a particular GMCH
configuration. This register can be updated by the GMCH -specific BIOS configuration sequence
before the PCI standard bus enumeration sequence. If the register is not updated then a default
value will select an aperture of maximum size (i.e., 256 MB). The size of the table that will
correspond to a 256 MB aperture is not practical for most applications and therefore these bits
must be programmed to a smaller practical value that will force adequate address range to be
requested via APBASE register from the PCI configuration software.
Bit
7:6
5:0
Description
Reserved
Graphics Aperture Size (APSIZE). Each bit in APSIZE[5:4] operates on similarly ordered bits in
APBASE[27:26] of the Aperture Base configuration register. When a particular bit of this field is 0 it
forces the similarly ordered bit in APBASE[27:26] to behave as 0. When a particular bit of this field is set
to 1 it allows corresponding bit of the APBASE[27:26] to be read/write accessible.
Only the following combinations are allowed when the Aperture is enabled:
Bits[5:4] Aperture Size
11 64 MB
10 128 MB
00 256 MB
Default for APSIZE[5:4]=00b forces default APBASE[27:26] =00b (i.e. all bits respond as hardwired to 0).
This provides maximum aperture size of 256 MB. As another example, programming APSIZE[5:4]=11b
enables APBASE[27:26] as read/write programmable providing a minimum size of 64 MB.
3:0: Reserved set to zero for software compatibility.
Datasheet
83