RG82855GMESL72L Datasheet, PDF (107/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
Bit
4
3
2
1
0
Description
Memory Write and Invalidate Enable (MWIE): The GMCH will never issue Memory Write and
Invalidate commands. This bit is therefore hardwired to 0. Writes to this bit position will have no effect.
Special Cycle Enable (SCE): The GMCH does not implement this bit and it is hardwired to a 0. Writes
to this bit position have no effect.
Bus Master Enable (BME): The GMCH is always enabled as a master on HI. This bit is hardwired to a
1. Writes to this bit position have no effect.
Memory Access Enable (MAE): The GMCH always allows access to Main Memory. This bit is not
implemented and is hardwired to 1. Writes to this bit position have no effect.
I/O Access Enable (IOAE): This bit is not implemented in the GMCH and is hardwired to a 0. Writes to
this bit position have no effect.
4.10.4
PCISTS – PCI Status Register
Address Offset:
Default Value:
Access:
Size:
06-07h
0080h
Read Only, Read/WriteClear
16 bits
PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0’s PCI
Interface. Bit 14 is Read/Write clear. All other bits are Read Only. Since GMCH Device #0 does
not physically reside on PCI_A many of the bits are not implemented.
Bit
15
14
13
12
11
10:9
8
7
6:5
4
3:0
Description
Detected Parity Error (DPE): The GMCH does not implement this bit and it is hardwired to a 0. Writes
to this bit position have no effect.
Signaled System Error (SSE): The GMCH does not implement this bit and it is hardwired to a 0.
Writes to this bit position have no effect.
Received Master Abort Status (RMAS): The GMCH does not implement this bit and it is hardwired to
a 0. Writes to this bit position have no effect.
Received Target Abort Status (RTAS): The GMCH does not implement this bit and it is hardwired to a
0. Writes to this bit position have no effect.
Signaled Target Abort Status (STAS): The GMCH does not implement this bit and it is hardwired to a
0. Writes to this bit position have no effect.
DEVSEL Timing (DEVT): These bits are hardwired to "00". Writes to these bit positions have no affect.
Device #0 does not physically connect to PCI_A. These bits are set to "00" (fast decode) so that the
GMCH does not limit optimum DEVSEL timing for PCI_A.
Master Data Parity Error Detected (DPD): The GMCH does not implement this bit and it is hardwired
to a 0. Writes to this bit position have no effect.
Fast Back-to-Back (FB2B): This bit is hardwired to 1. Writes to these bit positions have no effect.
Device #0 does not physically connect to PCI_A. This bit is set to 1 (indicating fast back-to-back
capability) so that the GMCH does not limit the optimum setting for PCI_A.
Reserved
Capability List (CLIST): This bit is hardwired to 0 to indicate to the configuration software that this
device/function does not implement new capabilities.
Reserved
Datasheet
107