RG82855GMESL72L Datasheet, PDF (37/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Signal Descriptions
R
Signal Name
GIRDY#
GTRDY#
GSTOP#
GDEVSEL#
GREQ#
Type
I/O
AGP
I/O
AGP
I/O
AGP
I/O
AGP
I
AGP
Description
G_IRDY#: Initiator Ready.
During PIPE# and SBA Operation: Not used while enqueueing requests via AGP
SBA and PIPE#, but used during the data phase of PIPE# and SBA transactions.
During FRAME# Operation: G_IRDY# is an output when GMCH acts as a FRAME#-
based AGP initiator and an input when the GMCH acts as a FRAME#-based AGP
target. The assertion of G_IRDY# indicates the current FRAME#-based AGP bus
initiator's ability to complete the current data phase of the transaction.
During Fast Write Operation: In Fast Write mode, G_IRDY# indicates that the AGP-
compliant master is ready to provide all write data for the current transaction. Once
G_IRDY# is asserted for a write operation, the master is not allowed to insert wait
states. The master is never allowed to insert a wait state during the initial data transfer
(32 bytes) of a write transaction. However, it may insert wait states after each 32-byte
block is transferred.
G_TRDY#: Target Ready.
During PIPE# and SBA Operation: Not used while enqueueing requests via AGP
SBA and PIPE#, but used during the data phase of PIPE# and SBA transactions.
During FRAME# Operation: G_TRDY# is an input when the GMCH acts as an AGP
initiator and is an output when the GMCH acts as a FRAME#-based AGP target. The
assertion of G_TRDY# indicates the target’s ability to complete the current data phase
of the transaction.
During Fast Write Operation: In Fast Write mode, G_TRDY# indicates the AGP-
compliant target is ready to receive write data for the entire transaction (when the
transfer size is less than or equal to 32 bytes) or is ready to transfer the initial or
subsequent block (32 bytes) of data when the transfer size is greater than 32 bytes.
The target is allowed to insert wait states after each block (32 bytes) is transferred on
write transactions.
G_STOP#: Stop.
During PIPE# and SBA Operation: This signal is not used during PIPE# or SBA
operation.
During FRAME# Operation: G_STOP# is an input when the GMCH acts as a
FRAME#-based AGP initiator and is an output when the GMCH acts as a FRAME#-
based AGP target. G_STOP# is used for disconnect, retry, and abort sequences on
the AGP interface.
G_ DEVSEL#: Device Select.
During PIPE# and SBA Operation: This signal is not used during PIPE# or SBA
operation.
During FRAME# Operation: G_DEVSEL#, when asserted, indicates that a FRAME#-
based AGP target device has decoded its address as the target of the current access.
The GMCH asserts G_DEVSEL# based on the DDR SDRAM address range being
accessed by a PCI initiator. As an input, G_DEVSEL# indicates whether the AGP
master has recognized a PCI cycle to it.
G_REQ#: Request.
During SBA Operation: This signal is not used during SBA operation.
During PIPE# and FRAME# Operation: G_REQ#, when asserted, indicates that the
AGP master is requesting use of the AGP interface to run a FRAME#- or PIPE#-based
operation.
Datasheet
37