RG82855GMESL72L Datasheet, PDF (128/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Intel® 855GM/GME GMCH System Address Map
R
5.4
Main System Memory Address Range (0010_0000h
to Top of Main Memory)
The address range from 1 MB to the top of main system memory is mapped to main DDR
SDRAM address range controlled by the GMCH. The GMCH will forward all accesses to
addresses within this range to the DDR SDRAM unless a hole in this range is created using the
fixed hole as controlled by the FDHC register. Accesses within this hole are forwarded to Hub
interface.
The GMCH provides a maximum DDR SDRAM address decode space of 4-GB. The GMCH
does not remap APIC memory space. The GMCH does not limit DDR SDRAM address space in
hardware.
5.4.1
15-MB – 16-MB Window
A hole can be created at 15 MB-16 MB as controlled by the fixed hole enable (FDHC register) in
Device 0 space. Accesses within this hole are forwarded to the Hub interface. The range of
physical DDR SDRAM disabled by opening the hole is not remapped to the Top of the memory –
that physical DDR SDRAM space is not accessible. This 15 MB-16 MB hole is an optionally
enabled ISA hole. Video accelerators originally used this hole. Validation and customer SV teams
also use it for some of their test cards. That is why it is being supported. There is no inherent
BIOS request for the 15-16 hole.
5.4.2 Pre-allocated System Memory
Voids of physical addresses that are not accessible as general system memory and reside within
system memory address range (< TOM) are created for SMM-mode and legacy VGA graphics
compatibility. It is the responsibility of BIOS to properly initialize these regions. The number
of UMA options has been extended. Allocation is at a fixed address in terms of rigid positioning
of UMA system memory ÆTOM-TSEG-UMA(size), but it is mapped at any available address by
a PCI allocation algorithm. GMADR and MMADR are requested through BARs.
The following table details the location and attributes of the regions.
Table 33. Pre-allocated System Memory
System Memory Segments
00000000H - 03E7FFFFH
03E80000H - 03F7FFFFH
03F80000H - 03FFFFFFH
03F80000H - 03FFFFFFH
Attributes
R/W
R/W
SMM Mode Only - CPU Reads
SMM Mode Only - CPU Reads
Comments
Available system memory 62.5 -MB
Pre-allocated Graphics VGA memory
1-MB (or 4/8/16/32- MB) when IGD is
enabled
TSEG Address Range
TSEG Pre-allocated system memory
128
Datasheet