RG82855GMESL72L Datasheet, PDF (28/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Intel® 855GM/855GME Chipset GMCH Overview
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Table 2. Intel^® 855GM/855GME GMCH Interface Clocks
Interface
Clock Speed
CPU System Bus
Frequency Ratio
Samples
Per Clock
CPU Bus
100 MHz
Reference
4
DDR SDRAM
100 MHz
133 MHz
166 MHz
1:1 Synchronous
2
1:1 Synchronous
2
1:1 Synchronous
2
LVDS Flat Panel 35 MHz-112
Asynchronous
1
MHz (single
channel)
DVO B or DVO C Up to 165 MHz
Asynchronous
2
DVO B+DVO C
Up to 330 MHz
Asynchronous
2
DAC Interface
350 MHz
Asynchronous
1
Data Rate
(Mega-
samples/s)
400
200
266
333
112
330
660
350
Data
Width
(Bytes)
8
8
8
8
2.25
1.5
3
3
Peak
Bandwidth
(MB/s)
3200
1600
2128
2664
252
495
1980
1050
2.10
System Interrupts
The GMCH supports both the legacy Intel 8259 Programmable Interrupt delivery mechanism and
the Intel Pentium M processor and Intel Celeron M processor FSB interrupt delivery mechanism.
The serial APIC Interrupt mechanism is not supported.
The Intel 8259 Interrupt delivery mechanism support consists of flushing in bound Hub interface
write buffers when an Interrupt Acknowledge cycle is forwarded from the system bus to the Hub
interface.
PCI MSI interrupts are generated as memory writes. The GMCH decodes upstream memory
writes to the range 0FEE0_0000h - 0FEEF_FFFFh from the Hub interface as message based
interrupts. The GMCH forwards the memory writes along with the associated write data to the
system bus as an Interrupt Message transaction. Since this address does not decode as part of
main system memory, the write cycle and the write data do not get forwarded to system memory
via the write buffer. The GMCH provides the response and HTRDY# for all Interrupt Message
cycles including the ones originating from the GMCH. The GMCH also supports interrupt
redirection for upstream interrupt memory writes.
For message based interrupts, system write buffer coherency is maintained by relying on strict
ordering of memory writes. The GMCH ensures that all memory writes received from a given
interface prior to an interrupt message memory write are delivered to the system bus for snooping
in the same order that they occur on the given interface.
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Datasheet