RG82855GMESL72L Datasheet, PDF (53/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
4.3
4.4
4.4.1
Standard PCI Bus Configuration Mechanism
The PCI Bus defines a slot based “configuration space” that allows each device to contain up to
eight functions with each function containing up to 256, 8-bit configuration registers. The PCI
Specification defines two bus cycles to access the PCI Configuration Space: Configuration Read
and Configuration Write. Memory and I/O spaces are supported directly by the CPU.
Configuration Space is supported by a mapping mechanism implemented within the GMCH. The
PCI 2.2 specification defines two mechanisms to access Configuration Space: Mechanism #1 and
Mechanism #2. The GMCH supports only Mechanism #1.
The Configuration Access Mechanism makes use of the CONFIG_ADDRESS register (at I/O
address 0CF8h though 0CFBh) and CONFIG_DATA register (at I/O address 0CFCh though
0CFFh). To reference a Configuration register a Dword I/O Write cycle is used to place a value
into CONFIG_ADDRESS that specifies the PCI Bus, the device on that bus, the function within
the device, and a specific Configuration register of the device function being accessed.
CONFIG_ADDRESS[31] must be a 1 to enable a Configuration cycle. CONFIG_DATA then
becomes a window into the four Bytes of Configuration Space specified by the contents of
CONFIG_ADDRESS. Any Read or Write to CONFIG_DATA will result in the GMCH
translating the CONFIG_ADDRESS into the appropriate Configuration cycle.
The GMCH is responsible for translating and routing the CPU’s I/O accesses to the
CONFIG_ADDRESS and CONFIG_DATA registers to internal GMCH Configuration registers
and to the Hub interface, or AGP_PCI_B.
Routing Configuration Accesses
The GMCH supports one bus interface: the Hub interface. PCI Configuration cycles are
selectively routed to this interface. The GMCH is responsible for routing PCI Configuration
cycles to the proper interface. PCI configuration cycles to the ICH4-M internal devices, and
Primary PCI (including downstream devices) are routed to the ICH4-M via the Hub interface.
AGP/PCI_B configuration cycles are routed to AGP. The AGP/PCI_B interface is treated as a
separate PCI bus from the configuration point of view. Routing of configuration AGP/PCI_B is
controlled via the standard PCI-to-PCI bridge mechanism using information contained within the
Primary bus number, the Secondary bus number, and the Subordinate bus number registers of the
corresponding PCI-to-PCI bridge device.
PCI Bus #0 Configuration Mechanism
The GMCH decodes the Bus Number (bits 23:16) and the Device Number fields of the
CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0, then the
Configuration cycle is targeting a PCI Bus #0 device.
The Host-Hub Interface Bridge entity within the GMCH is hardwired as Device #0 on PCI Bus
#0.
Configuration cycles to any of the GMCH’s internal devices are confined to the GMCH and not
sent over Hub interface. Accesses to disabled GMCH internal devices will be forwarded over the
Hub interface as Type 0 Configuration cycles.
Datasheet
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