RG82855GMESL72L Datasheet, PDF (76/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
Bit
5
4:2
1
0
Description
SERR on Receiving Unimplemented Special Cycle Hub Interface Completion Packet:
1 = The GMCH generates an SERR Hub Interface Special cycle when a GMCH initiated Hub interface
request is terminated with a Unimplemented Special cycle completion packet.
0 = Reporting of this condition is disabled.
Reserved
SERR on Multiple-bit ECC Error:
1 = For systems that support ECC, this field must be set to 1.
0 = Reserved
SERR on Single-bit ECC Error:
1 = For systems that support ECC, this field must be set to 1.
0 = Reserved
4.8.22
SMICMD – SMI Error Command Register (Device #0)
Address Offset:
Default Value:
Access:
Size:
66h
00h
Read/Write
8 bits
This register enables various errors to generate an SMI Hub Interface Special cycle. When an
Error Flag is set in the ERRSTS register, it can generate a SERR, SMI, or SCI Hub Interface
Special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers respectively.
Note: An error can generate one and only one Hub Interface Error Special cycle. It is software’s
responsibility to make sure that when an SMI Error Message is enabled for an error condition,
SERR, and SCI Error Messages are disabled for that same error condition.
Bit
7:4
3
2
1
0
Description
Reserved
SMI on GMCH Thermal Sensor Trip:
1 = An SMI Hub Interface Special cycle is generated by GMCH when the Thermal Sensor Trip requires
an SMI. A Thermal Sensor Trip Point cannot generate more than one special cycle.
Reserved
SMI on Multiple-bit ECC Error:
1 = For systems that support ECC, this field must be set to 1.
0 = Reserved
SMI on Single-bit ECC Error:
1 = For systems that support ECC, this field must be set to 1.
0 = Reserved
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Datasheet