RG82855GMESL72L Datasheet, PDF (108/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
4.10.5
RID – Revision Identification Register
Address Offset:
Default Value:
Access:
Size:
08h
02h
Read Only
8 bits
This register contains the revision number of the Intel 855GM/GME GMCH. These bits are Read
Only and Writes to this register have no effect.
Bit
7:0
Description
Revision Identification Number (RID): This is an 8-bit value that indicates the revision identification
number for the GMCH.
4.10.6
SUBC – Sub-Class Code Register
Address Offset:
Default Value:
Access:
Size:
0Ah
80h
Read Only
8 bits
This register contains the Sub-Class Code for the Intel 855GM/GME GMCH Device #0. This
code is 80h indicating a peripheral device.
Bit
7:0
Description
Sub-Class Code (SUBC): This is an 8-bit value that indicates the category of Bridge into which GMCH
falls. The code is 80h indicating other peripheral device.
4.10.7
BCC – Base Class Code Register
Address Offset:
Default Value:
Access:
Size:
0Bh
08h
Read Only
8 bits
This register contains the Base Class Code of the Intel 855GM/GME GMCH Device #0 Function
#3. This code is 08h indicating a peripheral device.
Bit
7:0
Description
Base Class Code (BASEC): This is an 8-bit value that indicates the Base Class code for the GMCH.
This code has the value 08h, indicating other peripheral device.
108
Datasheet