RG82855GMESL72L Datasheet, PDF (38/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Signal Descriptions
R
Signal Name
GGNT#
GAD[31:0]
GCBE#[3:0]
GPAR
Type
O
AGP
I/O
AGP
I/O
AGP
I/O
AGP
Description
G_GNT#: Grant.
During SBA, PIPE# and FRAME# Operation: G_GNT#, along with the information on
the ST[2:0] signals (status bus), indicates how the AGP interface will be used next.
Refer to the AGP Interface Specification, Revision 2.0 for further explanation of the
ST[2:0] values and their meanings.
G_AD[31:0]: Address/Data Bus.
During PIPE# and FRAME# Operation: The G_AD[31:0] signals are used to transfer
both address and data information on the AGP interface.
During SBA Operation: The G_AD[31:0] signals are used to transfer data on the AGP
interface.
Command/Byte Enable.
During FRAME# Operation: During the address phase of a transaction, the
G_CBE[3:0]# signals define the bus command. During the data phase, the
G_CBE[3:0]# signals are used as byte enables. The byte enables determine which
byte lanes carry meaningful data. The commands issued on the G_CBE# signals
during FRAME#-based AGP transactions are the same G_CBE# command described
in the PCI 2.2 specification.
During PIPE# Operation: When an address is enqueued using PIPE#, the C/BE#
signals carry command information. The command encoding used during PIPE#-based
AGP is different than the command encoding used during FRAME#-based AGP cycles
(or standard PCI cycles on a PCI bus).
During SBA Operation: These signals are not used during SBA operation.
Parity.
During FRAME# Operation: G_PAR is driven by the GMCH when it acts as a
FRAME#-based AGP initiator during address and data phases for a write cycle, and
during the address phase for a read cycle. G_PAR is driven by the GMCH when it acts
as a FRAME#-based AGP target during each data phase of a FRAME#-based AGP
memory read cycle. Even parity is generated across G_AD[31:0] and G_CBE[3:0]#.
During SBA and PIPE# Operation: This signal is not used during SBA and PIPE#
operation.
PCIRST# from the ICH4-M is assumed to be connected to RSTIN# and is used to reset AGP
interface logic within the GMCH. The AGP agent will also typically use PCIRST# provided by
the ICH4-M as an input to reset its internal logic.
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Datasheet