RG82855GMESL72L Datasheet, PDF (40/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Signal Descriptions
R
Signal Name
DVOCCLK
DVOCCLK#
Type
O
DVO
DVOBCCLKINT
I
DVO
DPMS
I
DVO
DAC Clocking
DREFCLK
I
LVTTL
LVDS LCD Flat Panel Clocking
DREFSSCLK
I
LVTTL
Description
Differential DVO Clock Output: These pins provide a differential pair reference
clock that can run up to 165 MHz.
DVOCCLK corresponds to the primary clock out.
DVOCCLK# corresponds to the primary complementary clock out.
DVOCCLK and DVOCCLK# should be left as NC (“Not Connected”) if the DVO C
port is not implemented.
DVOBC Pixel Clock Input/Interrupt: This signal may be selected as the reference
input to either dot clock PLL (DPLL) or may be configured as an interrupt input. A
TV-out device can provide the clock reference. The maximum input frequency for
this signal is 85 MHz.
DVOBC Pixel Clock Input: When selected as the dot clock PLL (DPLL) reference
input, this clock reference input supports SSC clocking for DVO LVDS devices.
DVOBC Interrupt: When configured as an interrupt input, this interrupt can support
either DVOB or DVOC.
DVOBCCLKINT needs to be pulled down if the signal is NOT used.
Display Power Management Signaling: This signal is used only in mobile systems
to act as the DREFCLK in certain power management states(i.e. Display Power
Down Mode); DPMS Clock is used to refresh video during S1-M. Clock Chip is
powered down in S1-M. DPMS should come from a clock source that runs during
S1-M and needs to be 1.5 V. So, an example would be to use a 1.5 V version of
SUSCLK from ICH4-M.
Display Clock Input: This pin is used to provide a 48 MHz input clock to the
Display PLL that is used for 2D/Video and DAC.
Display SSC Clock Input: This pin provides a 48 MHz or 66 MHz input clock (SSC
or non-SSC) to the Display PLL B.
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Datasheet