RG82855GMESL72L Datasheet, PDF (116/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
4.11.5
RID – Revision Identification Register (Device #2)
Address Offset:
Default Value:
Access:
Size:
08h
02h
Read Only
8 bits
This register contains the revision number of the IGD. These bits are Read Only and Writes to
this register have no effect.
Bit
Description
7:0 Revision Identification Number: This is an 8-bit value that indicates the revision identification number for
the GMCH.
4.11.6
CC – Class Code Register (Device #2)
Address Offset:
Default Value:
Access:
Size:
09−0Bh
030000h
Read Only
24 bits
This register contains the device programming interface information related to the Sub-Class code
and Base Class code definition for the IGD. This register also contains the Base Class code and
the function sub-class in relation to the Base Class code.
Bit
23:16
15:8
7:0
Description
Base Class Code (BASEC): 03=Display controller
Sub-Class Code (SCC):
Function 0: 00h=VGA compatible or 80h=Non VGA
Function 1: 80h=Non VGA
Programming Interface (PI): 00h=Hardwired as a Display controller.
4.11.7
CLS – Cache Line Size Register (Device #2)
Address Offset:
Default Value:
Access:
Size:
0Ch
00h
Read only
8 bits
The IGD does not support this register as a PCI slave.
Bit
7:0 Cache Line Size (CLS) – RO
Description
116
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