RG82855GMESL72L Datasheet, PDF (80/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
4.8.26
AGPSTAT – AGP Status Register (Device #0)
Address Offset:
Default Value:
Access:
Size:
A4–A7h
1F000217h
Read Only
32 bits
This register reports AGP device capability/status.
Bit
31:24
23:10
9
8:6
5
4
3
2:0
Description
Request (RQ). Indicates a maximum of 32 outstanding AGP command requests can be handled by the
GMCH .
Default =1Fh to allow a maximum of 32 outstanding AGP command requests.
Reserved
Side Band Addressing (SBA). Indicates that the GMCH supports side band addressing.
Reserved
Address Support Above 4 GB (4 GB). Indicates that the GMCH does not support addresses greater
than 4 gigabytes.
Fast Writes.
1 = The GMCH supports Fast Writes from the CPU to the AGP master. (Default)
Reserved
RATE. After reset the GMCH reports its data transfer rate capability. Bit 0 identifies if AGP device
supports 1X data transfer mode, bit 1 identifies if AGP device supports 2X data transfer mode, bit 2
identifies if AGP device supports 4X data transfer mode. 1X , 2X , and 4X data transfer modes are
supported by the GMCH and therefore this bit field has a Default Value = 111.
NOTE: The selected data transfer mode applies to both AD bus and SBA bus.
80
Datasheet