RG82855GMESL72L Datasheet, PDF (110/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
4.10.11
CAPPTR – Capabilities Pointer Register
Address Offset:
Default Value:
Access:
Size:
34h
00h
Read Only
8 bits
The CAPPTR provides the offset that is the pointer to the location of the first device capability in
the capability list.
Bit
7:0
Description
Pointer to the offset of the first capability ID register block: In this case there are no capabilities
therefore these bits are hardwired to 00h to indicate the end of the capability-linked list.
4.10.12
HPLLCC – HPLL Clock Control Register (Device #0)
Address Offset:
Default Value:
Access:
Size:
C0–C1h
00h
Read Only
16 bits
Bit
15:11
10
9
8
7:2
1:0
Description
Reserved
HPLL VCO Change Sequence Initiate Bit:
Software must Write a 0 to clear this bit and then Write a 1 to initiate sequence again.
Hphase Reset Bit:
1 = Assert
0 = Deassert (default)
Reserved
Reserved
HPLL Clock Control:
Software is allowed to update this register.
See
Table 29 below.
110
Datasheet