RG82855GMESL72L Datasheet, PDF (95/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
Bit
27:26
25
24:15
Description
Back To Back Read-Write commands spacing (DDR, same or different Rows/Bank): This field
determines the RD-WR command spacing, in terms of common clocks based on the following formula:
CL + 0.5xBL + TA (RD-WR) – DQSS
DQSS: is time from Write command to data and is always 1 CK
BL: is Burst Length which is set to 4
TA (RD-WR): is required DQ turn-around, can be set to 1, 2 or 3 CK
CL: is CAS latency, can be set to 2 or 2.5
Examples of usage:
For BL=4, with single DQ turn-around and CL=2, this field must be set to 4 CK (2+2+1-1)
Encoding CK between RD and WR commands
00:
7
01:
6
10:
5
11:
4
NOTE: Since reads in DDR SDRAM cannot be terminated by Writes, the Space between commands is
not a function of Cycle Length but of Burst Length.
Back To Back Read-Read commands spacing (DDR, different Rows):
This field determines the RD-RD Command Spacing, in terms of common clocks based on the following
formula: 0.5xBL + TA(RD-RD)
BL: is Burst Length and can be set to 4.
TA (RD-RD): is required DQ turn-around, can be set to 1 or 2 CK
Examples of usage:
For BL=4, with single DQ turn-around, this field must be set to 3 CK (2+1)
Encoding CK between RD and RD commands
0:
4
1:
3
NOTE: Since a Read to a different row does not terminate a Read, the Space between commands is not
a function of Cycle Length but of Burst Length.
Reserved
Datasheet
95