RG82855GMESL72L Datasheet, PDF (63/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
4.8.5
4.8.6
4.8.7
RID – Register Identification
Address Offset:
Default Value:
Access:
Size:
08h
02h
Read Only
8 bits
This register contains the revision number of the GMCH Device #0. These bits are read only and
writes to this register have no effect.
Bit
7:0
Description
Revision Identification Number (RID): This is an 8-bit value that indicates the revision identification
number for the GMCH Device #0.
SUBC – Sub Class Code Register
Address Offset:
Default Value:
Access:
Size:
0Ah
00h
Read Only
8 bits
This register contains the Sub-Class Code for the GMCH Device #0. This code is 00h indicating a
Host Bridge device.
Bit
7:0
Description
Sub-Class Code (SUBC): This is an 8-bit value that indicates the category of Bridge into which the
GMCH falls. The code is 00h indicating a Host Bridge.
BCC – Base Class Code Register
Address Offset:
Default Value:
Access:
Size:
0Bh
06h
Read Only
8 bits
This register contains the Base Class code of the GMCH Device #0. This code is 06h indicating a
Bridge device.
Bit
7:0
Description
Base Class Code (BASEC): This is an 8-bit value that indicates the Base Class Code for the GMCH.
This code has the value 06h, indicating a Bridge device.
Datasheet
63