RG82855GMESL72L Datasheet, PDF (24/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Intel® 855GM/855GME Chipset GMCH Overview
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2.2
2.3
Processor Host Interface
The Intel 855GM/855GME GMCH is optimized for the Intel Pentium M processor and Intel
Celeron M processor
Key features of the front side bus (FSB) are:
• Support for a 400 MHz system bus frequency.
• Source synchronous double pumped address (2X)
• Source synchronous quad pumped data (4X)
• Front side bus interrupt delivery
• Low voltage swing Vtt (1.05V)
• Dynamic Power Down (DPWR#) support
• Integrates AGTL+ termination resistors on all of the AGTL+ signals
• Supports 32-bit host bus addressing allowing the CPU to access the entire 4 GB of the
GMCH memory address space.
• An 8-deep, In-Order queue
• Support DPWR# signal
• Supports one outstanding defer cycle at a time to any particular I/O interface
GMCH System Memory Interface
The GMCH system memory controller directly supports the following:
• One channel of PC1600/2100 SO-DIMM DDR SDRAM memory (Intel 855GM GMCH)
• One channel of PC1600/2100/2700 SO-DIMM DDR SDRAM memory (Intel 855GME
GMCH)
• DDR SDRAM devices with densities of 128-Mb, 256-Mb, and 512-Mb technology
• Up to 1 GB (512-Mb technology) with two SO-DIMMs
• Up to 2 GB (512-Mb technology) using high density devices with two SO-DIMMs
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Datasheet