RG82855GMESL72L Datasheet, PDF (58/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
Bit
31:0
Descriptions
Configuration Data Window (CDW). If bit 31 of CONFIG_ADDRESS is 1, then any I/O access to
the CONFIG_DATA register will be mapped to Configuration Space using the contents of
CONFIG_ADDRESS.
4.7
VGA I/O Mapped Registers
If Device #2 is enabled, and Function #0 within Device #2 is enabled for VGA, and IO_EN is set
within Function #0 then GMCH claims a set of I/O registers for legacy VGA function. Table 22
lists direct CPU Access registers and Table 23 lists registers that are Index – Data registers that
are used to access Internal VGA registers.
Table 22. VGA I/O Mapped Register List
Name
ST00
ST01
FCR
MSR
Function
VGA Input Status Register 0
VGA Input Status Register 1
VGA Feature Control Register
VGA Miscellaneous Status/Output Register
Read @
3C2h
3BAh/3Dah
3CAh
3CCh
Write @
⎯
⎯
3BAh/3DAh
3C2h
Table 23. Index – Data Registers
Name
SRX
GRX
ARX
Function
Sequencer Registers
Graphics Controller Registers
Attribute Control Registers
DACMASK
DACSTATE
DACRX
DACWX
DACDATA
CRX
Pixel Data Mask Register
DAC State Register
Palette Read Index Register
Palette Write Index Register
Palette Data Register
CRT Registers
Index IO
3C4
3CE
3C0
--
--
3C7 Write Only
3C8 Write Only
3C9
3B4/3D4
(MDA/CGA)
Data IO
3C5
3CF
3C0: Write
3C1: Read
3C6h
3C7 Read Only
--
3B5/3D5
(MDA/CGA)
58
Datasheet