RG82855GMESL72L Datasheet, PDF (32/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Signal Descriptions
R
Signal Name
RS[2:0]#
Type
O
AGTL+
Description
Response Status: Indicates the type of response according to the following the table:
RS[2:0]#
Response type
000
Idle state
001
Retry response
010
Deferred response
011
Reserved (not driven by GMCH)
100
Hard Failure (not driven by GMCH)
101
No data response
110
Implicit Write back
111
Normal data response
3.2
DDR SDRAM Interface
Table 4. DDR SDRAM Interface Descriptions
Signal Name
SCS[3:0]#
SMA[12:0]
SBA[1:0]
SRAS#
SCAS#
SWE#
SDQ[71:0]
Type
O
SSTL_2
O
SSTL_2
O
SSTL_2
O
SSTL_2
O
SSTL_2
O
SSTL_2
I/O
SSTL_2
Description
Chip Select: These pins select the particular DDR SDRAM components during the
active state.
NOTE: There is one SCS# per DDR-SDRAM Physical SO-DIMM device row. These
signals can be toggled on every rising System Memory Clock edge (SCMDCLK).
Multiplexed Memory Address: These signals are used to provide the multiplexed row
and column address to the DDR SDRAM.
Bank Select (Memory Bank Address): These signals define which banks are selected
within each DDR SDRAM row. The SMA and SBA signals combine to address every
possible location within a DDR SDRAM device.
DDR Row Address Strobe: SRAS# may be heavily loaded and requires tw0 DDR
SDRAM clock cycles for setup time to the DDR SDRAMs. Used with SCAS# and SWE#
(along with SCS#) to define the system memory commands.
DDR Column Address Strobe: SCAS# may be heavily loaded and requires two clock
cycles for setup time to the DDR SDRAMs. Used with SRAS# and SWE# (along with
SCS#) to define the system memory commands.
Write Enable: Used with SCAS# and SRAS# (along with SCS#) to define the DDR
SDRAM commands. SWE# is asserted during writes to DDR SDRAM. SWE# may be
heavily loaded and requires two clock cycles for setup time to the DDR SDRAMs.
Data Lines: These signals are used to interface to the DDR SDRAM data bus.
NOTE: ECC error detection is supported: by the SDQ[71:64] signals.
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Datasheet