RG82855GMESL72L Datasheet, PDF (42/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Signal Descriptions
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3.6.2 Digital Video Output B (DVOB) Port
Table 13. Digital Video Output B (DVOB) Port Signal Descriptions
Name
DVOBD[11:0]
DVOBHSYNC
DVOBVSYNC
DVOBBLANK#
DVOBFLDSTL
Type
O
DVO
O
DVO
O
DVO
O
DVO
I
DVO
Description
DVOB Data: This data bus is used to drive 12-bit RGB data on each edge of the
differential clock signals, DVOBCLK and DVOBCLK#. This provides 24-bits of data per
clock period. In dual channel mode, this provides the lower 12-bits of pixel data.
DVOBD[11:0] should be left as left as NC (“Not Connected”) if not used.
Horizontal Sync: HSYNC signal for the DVOB interface.
DVOBHSYNC should be left as left as NC (“Not Connected”) if not used.
Vertical Sync: VSYNC signal for the DVOB interface.
DVOBVSYNC should be left as left as NC (“Not Connected”) if the signal is NOT used
when using internal graphics device.
Flicker Blank or Border Period Indication: DVOBBLANK# is a programmable output
pin driven by the GMCH.
When programmed as a blank period indication, this pin indicates active pixels excluding
the border. When programmed as a border period indication, this pin indicates active pixel
including the border pixels.
DVOBBLANK# should be left as left as NC (“Not Connected”) if not used.
TV Field and Flat Panel Stall Signal. This input can be programmed to be either a TV
Field input from the TV encoder or Stall input from the flat panel.
DVOB TV Field Signal: When used as a Field input, it synchronizes the overlay field with
the TV encoder field when the overlay is displaying an interleaved source.
DVOB Flat Panel Stall Signal: When used as the Stall input, it indicates that the pixel
pipeline should stall one horizontal line. The signal changes during horizontal blanking.
The panel fitting logic, when expanding the image vertically, uses this.
DVOBFLDSTL needs to be pulled down if not used.
3.6.3
Intel^® 855GME GMCH DVO/I²C to AGP Pin Mapping
The GMCH will mux a DVODETECT signal with the GPAR signal on the AGP bus. This signal
will act as a strap and indicate whether the interface is in AGP or DVO mode. The GMCH has an
internal 8.2-k pull-up on this signal that will naturally pull it high. If an AGP graphics device is
present, the signal will be pulled low at the AGP graphics device and the AGP/DVO mux select
bit in the SHIC register will be set to AGP mode. Boards that do not use an AGP graphics device
should have a pull-down resistor on DVODETECT if they have digital display devices connected
to the AGP/DVO interface. SBA[7:0] will act as straps for an ADDID. When an AGP graphics
device is present, DVODETECT=1 (AGP mode),
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