RG82855GMESL72L Datasheet, PDF (70/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
Bits [7, 3]
Reserved
X
Bits [6, 2]
Reserved
X
Bits [5, 1]
WE
1
Bits [4, 0]
RE
1
Description
Read/Write. This is the normal operating mode
of main system memory. Both Read and Write
cycles from the host are claimed by the GMCH
and forwarded to DDR SDRAM. The GMCH will
respond as a Hub interface target for both Read
and Write accesses.
As an example, consider a BIOS that is implemented on the Expansion bus. During the
initialization process, the BIOS can be shadowed in main system memory to increase the system
performance. When BIOS is shadowed in main system memory, it should be copied to the same
address location. To shadow the BIOS, the attributes for that address range should be set to Write
Only. The BIOS is shadowed by first doing a Read of that address. This Read is forwarded to the
Expansion bus. The Host then does a Write of the same address, which is directed to main system
memory. After the BIOS is shadowed, the attributes for that system memory area are set to Read
Only so that all Writes are forwarded to the Expansion bus. Figure 5 and Table 26 show the PAM
registers and the associated attribute bits.
Figure 5. PAM Registers
PAM6
PAM5
PAM4
PAM3
PAM2
PAM1
PAM0
Offset
5Fh
5Eh
5Dh
5Ch
5Bh
5Ah
59h
76 5 4
R R WE RE
Reserved
Reserved
Write Enable (R/W)
1=Enable
0=Disable
Read Enable (R/W)
1=Enable
0=Disable
3 21 0
R R WE RE
Read Enable (R/W)
1=Enable
0=Disable
Write Enable (R/W)
1=Enable
0=Disable
Reserved
Reserved
pam
70
Datasheet