RG82855GMESL72L Datasheet, PDF(51/213 Page) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

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RG82855GMESL72L Datasheet, PDF (51/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

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4 Register Description

4.1

Conceptual Overview of the Platform Configuration

Structure

The Intel 855GM GMCH and ICH4-M are physically connected by Hub interface. From a

configuration standpoint, the Hub interface is logically PCI bus #0. As a result, all devices

internal to the GMCH and ICH4-M appear to be on PCI bus #0. The systemâs primary PCI

expansion bus is physically attached to the ICH4-M and from a configuration perspective, appears

to be a hierarchical PCI bus behind a PCI-to-PCI bridge and therefore has a programmable PCI

Bus number. Note that the primary PCI bus is referred to as PCI_A in this document and is not

PCI bus #0 from a configuration standpoint. For the Intel 855GME GMCH, the AGP appears to

system software to be real PCI bus behind PCI-to-PCI bridges resident as devices on PCI bus #0.

The GMCH contains two PCI devices within a single physical component. The configuration

registers for the two devices are mapped as devices residing on PCI bus #0.

Device #0: Host-Hub Interface Bridge/DDR SDRAM Controller. Logically this appears as a PCI

device residing on PCI bus #0. Physically, Device #0 contains the standard PCI registers, DDR

SDRAM registers, the Graphics Aperture Controller registers, HI Control registers and other

GMCH specific registers. Device #0 is divided into the following functions:

Function #0: Host Bridge Legacy registers including Graphics Aperture Control registers, HI

Configuration registers and Interrupt Control registers

Function #1: DDR SDRAM Interface Registers

Function #3: Intel Configuration Process Registers

Device #2: Integrated Graphics Controller. Logically this appears as a PCI device residing on PCI

bus #0. Physically Device #2 contains the Configuration registers for 2D, 3D, and display

functions.

Table 20 shows the Device # assignment for the various internal GMCH devices.

Table 20. Device Number Assignment

GMCH Function

Host-Hub interface, DDR SDRAM I/F, Legacy control

Host-to-AGP Bridge (Virtual PCI-to-PCI)

Integrated Graphics Controller (IGD)

Bus #0, Device#

Device #0

Device #1 (Intel 855GME GMCH Only)

Device #2

Datasheet

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