RG82855GMESL72L Datasheet, PDF (158/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Functional Description
R
Optionally the FIELD pin can indicate to the overlay which field is currently being displayed at
the display device.
6.5.2.10
Intel 855GME GMCH AGP Interface Overview
The GMCH support 1.5 V AGP 1X/2X/4X devices. The AGP signal buffers are 1.5 V
drive/receive (buffers are not 3.3 V tolerant). The GMCH support 2X/4X source synchronous
clocking transfers for read and write data, and sideband addressing. The GMCH also support 2X
and 4X clocking for Fast Writes initiated from the GMCH (on behalf of the processor).
AGP PIPE# or SBA[7:0] transactions to DRAM do not get snooped and are, therefore, not
coherent with the processor caches. AGP FRAME# transactions to DRAM are snooped. AGP
PIPE# and SBA[7:0] accesses to and from the hub interface are not supported. AGP FRAME#
access from an AGP master to the hub interface is also not supported. Only the AGP FRAME
memory writes from the hub interface are supported.
6.5.2.11 AGP Target Operations
As an initiator, the GMCH does not initiate cycles using AGP enhanced protocols. The GMCH
supports AGP cycles targeting interface to main memory only. The GMCH supports interleaved
AGP PIPE#] and AGP FRAME#, or AGP SBA[7:0] and AGP FRAME# transactions.
Table 39. AGP Commands Supported by the GMCH when Acting as an AGP Target
AGP Command
C/BE[3:0]#
Encoding
Read
0000
0000
Hi-Priority Read
0001
0000
Reserved
Reserved
Write
0010
0011
0100
0100
Hi-Priority Write
0101
0101
Reserved
Reserved
Long Read
0110
0111
1000
Cycle Destination
Main Memory
The Hub interface
Main Memory
The Hub interface
N/A
N/A
Main Memory
The Hub interface
Main Memory
The Hub interface
N/A
N/A
Main Memory
The Hub interface
GMCH Host Bridge
Response as PCIx Target
Low Priority Read
Complete locally with random data; does not go
to the hub interface
High Priority Read
Complete locally with random data; does not go
to the hub interface
No Response
No Response
Low Priority Write
Cycle goes to DRAM with BE’s inactive; does
not go to the hub interface
High Priority Write
Cycle goes to DRAM with BE’s inactive; does
not go to the hub interface
No Response
No Response
Low Priority Read
Complete locally with random data; does not go
to the hub interface
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Datasheet