RG82855GMESL72L Datasheet, PDF (84/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
4.8.31
ATTBASE – Aperture Translation Table Base Register
(Device #0)
Address Offset:
Default Value:
Access:
Size:
B8–BBh
00000000h
Read/Write
32 bits
This register provides the starting address of the Graphics Aperture Translation Table Base
located in the main DDR SDRAM. This value is used by the GMCH’s Graphics Aperture address
translation logic (including the GTLB logic) to obtain the appropriate address translation entry
required during the translation of the aperture address into a corresponding physical DDR
SDRAM address. The ATTBASE register may be dynamically changed.
The address provided via ATTBASE is 4 kB aligned.
Bit
31:12
11:0
Description
This field contains a pointer to the base of the translation table used to map memory space addresses
in the aperture range to addresses in main memory.
Reserved
4.8.32
AMTT – AGP Interface Multi-Transaction Timer Register
(Device #0)
Address Offset:
Default Value:
Access:
Size:
BCh
00h
Read/Write
8 bits
AMTT is an 8-bit register that controls the amount of time that the GMCH ’s arbiter allows
AGP/PCI master to perform multiple back-to-back transactions. The GMCH ’s AMTT
mechanism is used to optimize the performance of the AGP master (using PCI semantics) that
performs multiple back-to-back transactions to fragmented memory ranges (and as a consequence
it can not use long burst transfers). The AMTT mechanism applies to the CPU-AGP/PCI
transactions as well and it guarantees to the CPU a fair share of the AGP/PCI interface bandwidth.
The number of clocks programmed in the AMTT represents the guaranteed time slice (measured
in 66- MHz clocks) allotted to the current agent (either AGP/PCI master or Host bridge) after
which the AGP arbiter will grant the bus to another agent. The default value of AMTT is 00h and
disables this function. The AMTT value can be programmed with 8 clock granularity. For
example, if the AMTT is programmed to 18h, then the selected value corresponds to the time
period of 24 AGP (66 MHz) clocks.
Bit
7:3
2:0
Description
Multi-Transaction Timer Count Value. The number programmed in these bits represents the
guaranteed time slice (measured in eight 66 MHz clock granularity) allotted to the current agent (either
AGP/PCI master or Host bridge) after which the AGP arbiter will grant the bus to another agent.
Reserved.
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