RG82855GMESL72L Datasheet, PDF (90/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
4.9.5
RID – Revision Identification Register
Address Offset:
Default Value:
Access:
Size:
08h
02h
Read Only
8 bits
This register contains the revision number of the Intel 855GM/GME GMCH Device #0. These
bits are Read Only and Writes to this register have no effect.
Bit
7:0
Description
Revision Identification Number (RID): This is an 8-bit value that indicates the revision identification
number for the GMCH Device #0.
4.9.6
SUBC – Sub-Class Code Register
Address Offset:
Default Value:
Access:
Size:
0Ah
80h
Read Only
8 bits
This register contains the Sub-Class code for the Intel 855GM/GME GMCH Device #0. This code
is 80h indicating Other Peripheral device.
Bit
Descriptions
7:0
Sub-Class Code (SUBC): This is an 8-bit value that indicates the category of Peripheral device into
which the GMCH Function #1 falls. The code is 80h indicating Other Peripheral device.
4.9.7
BCC – Base Class Code Register
Address Offset:
Default Value:
Access:
Size:
0Bh
08h
Read Only
8 bits
This register contains the Base Class code of the Intel 855GM/GME GMCH Device #0 Function
#1. This code is 08h indicating Other Peripheral device.
Bit
7:0
Description
Base Class Code (BASEC): This is an 8-bit value that indicates the Base Class Code for the GMCH.
This code has the value 08h, indicating Other Peripheral device.
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Datasheet