RG82855GMESL72L Datasheet, PDF (186/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Video Filter Capacitors and Ferrite Bead Arranged in a
PI Configuration (One PI Filter Testability)
R
9.1
XOR Test Mode Entry
Figure 11. XOR Chain Test Mode Entry Events Diagram
p o w e ro k
VSYNC
HSYNC
LC LK C TLA
R S T IN # (P C I re s e t)
D o n 't c a re
D o n 't c a re
D o n 't c a re
NOTE: HSYNC and LCLKCTLA = XOR Chain Test Mode Activation; No clock is required for XOR Chain Test
Mode. A minimum of 50 ns PWROK assertion prior to RSTIN# assertion is recommended. A minimum
of 10 ns VSYNC/HSYNC/LCLKCTLA assertion prior to PWROK assertion is recommended.
Figure 12. ALLZ Test Mode Entry Events Diagram
pow erok
VSYNC
HSYNC
LC LK C TLA
R S T IN # (P C I re s e t)
D o n 't c a re
D o n 't c a re
D o n 't c a re
NOTE: VSYNC and LCLKCTLA = ALL Z Test Mode Activation; No clock is required for ALLZ Test Mode
Activation. A minimum of 50 ns PWROK assertion prior to RSTIN# assertion is recommended. A
minimum of 10 ns VSYNC/HSYNC/LCLKCTLA assertion prior to PWROK assertion is recommended.
186
Datasheet