RG82855GMESL72L Datasheet, PDF (26/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Intel® 855GM/855GME Chipset GMCH Overview
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Display Features
The Intel 855GM/855GME GMCH has four display ports, one analog and three digital. With
these interfaces, the GMCH can provide support for a progressive scan analog monitor, a
dedicated dual channel LVDS LCD panel, and two DVO devices. Each port can transmit data
according to one or more protocols. The data that is sent out the display port is selected from one
of the two possible sources, Pipe A or Pipe B.
GMCH Analog Display Port
Intel 855GM/855GME GMCH has an integrated 350 MHz, 24-bit RAMDAC that can directly
drive a progressive scan analog monitor pixel resolution up to 1600x1200 at 85-Hz refresh and up
to 2048x1536 at 75-Hz refresh. The Analog display port can be driven by Pipe A or Pipe B.
GMCH Integrated LVDS Port
The Intel 855GM/855GME GMCH have an integrated dual channel LFP Transmitter interface to
support LVDS LCD panel resolutions up to UXGA The display pipe provides panel up-scaling to
fit a smaller source image onto a specific native panel size, as well as provides panning and
centering support. The LVDS port is only supported on Pipe B. The LVDS port can only be
driven by Pipe B, either independently or simultaneously with the Analog Display port. Spread
Spectrum Clocking is supported: center and down spread support of 0.5%, 1%, and 2.5% utilizing
an external SSC clock.
GMCH Integrated DVO Ports
The DVO B/C interface is compliant with the DVI Specification 1.0. When combined with a DVI
compliant external device (e.g. TMDS Flat Panel Transmitter, TV-out encoder, etc.), the GMCH
provides a high-speed interface to a digital or analog display (e.g. flat panel, TV monitor, etc.).
The DVO ports are connected to an external display device. Examples of this are TV-out
encoders, external DACs, LVDS transmitters, and TMDS transmitters. Each display port has
control signals that may be used to control, configure and/or determine the capabilities of an
external device.
The GMCH provides two DVO ports that are each capable of driving a 165 MHz pixel clock at
the DVO B or DVO C interface. When DVO B and DVO C are combined into a single DVO port,
then an effective pixel rate of 330 MHz can be achieved. The DVO B/C ports can be driven by
Pipe A or Pipe B. If driven on Pipe B, then the LVDS port must be disabled.
Intel^® 855GME GMCH AGP Interface
The Intel 855GME has support for a single AGP component is supported by the AGP interface.
The AGP buffers operate only in 1.5 V mode. They are not 3.3 V tolerant.
The AGP interface supports 1X/2X/4X AGP signaling and 2X/4X Fast Writes. AGP semantic
cycles to DDR SDRAM are not snooped on the host bus. PCI semantic cycles to DDR SDRAM
are snooped on the host bus. The GMCH/MCH support PIPE# or SBA[7:0] AGP address
mechanisms, but not both simultaneously. Either the PIPE# or the SBA[7:0] mechanism must be
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Datasheet